1. Field of the Invention
The invention relates to computer system peripheral connections and more particularly to managing system interrupts.
2. Background
Peripheral Component Interconnect (PCI)-Extended Industry Standard Architecture (EISA) bridge sets provide an I/O subsystem for many computer systems. One Peripheral Component Interconnect (PCI) standard is PCI Local Bus standard version 2.2 (Jan. 5, 1999). The chip set generally consists of two components—the PCI-EISA Bridge (PCEB) and the EISA system component (ESC). In general, the ESC implements system functions such as timer-counter, direct memory access (DMA), and interrupt control.
In one form of interrupt control utilized in certain chip set configurations of Intel Corporation of Santa Clara, Calif., an EISA compatible interrupt controller of the ESC incorporates the functionality of two 82C59 interrupt controllers that are cascaded providing fourteen external and two internal interrupts. The ESC also contains an Advanced Programmable Interrupt Controller (APIC). The APIC can be used in either a uni-processor or multi-processor system. The APIC provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each system can have its own set of interrupts.
As noted, the EISA compatible interrupt controller incorporates the functionality of two 82C59 interrupt controllers. The two controllers are cascaded into a master interrupter controller and a slave interrupt controller. Two internal interrupts are used for internal function only and are not available at the chip periphery. One interrupt is used to cascade the two controllers together and another is used as a system timer interrupt. The remaining 14 interrupt lines are available for external system interrupts. The interrupts are programmed to utilize on the order of 2000 logic gates. Examples of uses of the 14 system interrupts include interrupts for a keyboard, hard drive, modem, etc.
While the standard EISA compatible interrupt controller is intended for use in a uni-processor system, the APIC can be used in either a uni-processor or multi-processor system. An APIC provides multi-processor interrupt management and incorporates static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts.
At the system level, an APIC consists of two parts—one residing in the I/O subsystem (I/O APIC) and the other in the CPU (local APIC). The ESC contains the I/O APIC unit.
The I/O APIC unit consists of a set of interrupt input signals, a 16-entry Interrupt Redirection. Table, programmable registers, and a message unit for sending and receiving APIC messages over the APIC bus. I/O devices inject interrupts into the system by asserting one of the interrupt lines to the I/O APIC. The I/O APIC selects a corresponding entry in the redirection table and uses the information of that entry to format an interrupt request message. Each entry in the redirection table can be individually programmed to indicate edge/level sensitive interrupt signals, the interrupt vector and priority, the destination processor, and how the processor is selected (e.g., statically or dynamically). The information in the table is used to transmit a message to other APIC units via the APIC bus.
In addition to its compatibility with multi-processor environments, the APIC system offers the ability to handle a greater number of system interrupts with greater flexibility than the EISA compatible interrupt controller. Nevertheless, the EISA compatible interrupt controller remains a legacy standard for interrupt control in the modern processor environment.